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Table of Contents

• ↓ Intel 4 Process Scales Logic with Design, Materials, and EUV
• ↓ Transistor Count: A Flawed Metric
• ↓ Power Delivery in a Modern Processor
• ↓ SuperComputing 19: HPC Meets Machine Learning
• ↓ MRAM Research at VLSI 2018
• ↓ IBM’s Machine Learning Accelerator at VLSI 2018
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"The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography. The first product, the Meteor Lake compute tile, will ramp to high volume manufacturing in 2023."

"Transistor count and transistor density are often portrayed as technical achievements and milestones. Many vendors brag about the complexity of their design, as measured by transistor count. In reality, transistor count and density varies considerably based on the type of chip and especially the type of circuitry within the chip, and there is no standard way of counting. The net result is that transistor count and density are only approximate metrics and focusing on those particular numbers risks losing sight of the bigger picture."

"Power delivery is one of the most significant challenges in modern processors. The power delivery network (PDN) must meet the demanding requirements of modern CMOS technology, supply power with excellent efficiency, and swiftly respond to changes in power draw."

"For me, SC19 was about the fusion of machine learning and scientific computing. I learned about new technologies from Nvidia, Graphcore, and Cerebras Systems and spoke on a panel about the role of MLPerf in benchmarking HPC systems for machine learning and the many lessons learned."

Key Topics & Focus Areas for realworldtech.com:

Intel 4 Process Scales Logic with Design, Materials, and EUV

Transistor Count: A Flawed Metric

Power Delivery in a Modern Processor

SuperComputing 19: HPC Meets Machine Learning

MRAM Research at VLSI 2018

IBM’s Machine Learning Accelerator at VLSI 2018